Methods of forming circuitry

ABSTRACT

In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; d) forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and e) at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer. In another aspect, the invention includes an integrated circuit comprising a capacitor and a conductive plug, the conductive plug and capacitor comprising a first common and continuous layer. In yet another aspect, the invention includes a circuit construction comprising: a) a substrate having a memory array region and a peripheral region that is peripheral to the memory array region; b) a capacitor construction over the memory array region of the substrate, the capacitor construction comprising a storage node, a capacitor dielectric layer and a cell plate layer; the capacitor dielectric layer being between the storage node and the cell plate layer; and c) an electrical interconnect over the peripheral region, the interconnect being electrically connected to the cell plate layer and extending between the cell plate layer and the substrate.

TECHNICAL FIELD

[0001] This invention pertains to semiconductive processing methods offorming integrated circuitry, as well as to semiconductive devicecircuitry.

BACKGROUND OF THE INVENTION

[0002] A common method of forming memory devices is to form an array ofdevices (a so-called memory array), and to form control devices at aperiphery of the array. The memory array can comprise, for example, adynamic random access memory (DRAM) array comprising arrays ofcapacitors and transistors. The peripheral circuitry can comprise, forexample, transistors. Frequently, the memory array circuitry and theperipheral circuitry will be covered by insulative materials. Conductivecontact plugs can be formed to extend through the insulative materialsto electrically connect peripheral circuitry and memory array circuitryto one another, or to other circuitry.

[0003] A continuing goal in semiconductor device fabrication is tominimize process steps. Accordingly, it would be desired to developprocessing methods which reduce processing steps associated with formingmemory array circuitry and peripheral circuitry.

SUMMARY OF THE INVENTION

[0004] In one aspect, the invention encompasses a method of formingcircuitry. A capacitor electrode is formed over one region of asubstrate and a conductive diffusion barrier layer is formed proximatethe electrode. A dielectric layer is formed. The diffusion barrier layeris between the electrode and the dielectric layer. A conductive plug isformed over another region of the substrate. The conductive plugcomprises a same material as the conductive diffusion barrier layer andat least a portion of the conductive plug is formed simultaneously withthe conductive diffusion barrier layer.

[0005] In another aspect, the invention encompasses an integratedcircuit comprising a capacitor and a conductive plug wherein theconductive plug and capacitor include a common and continuous layer.

[0006] In yet another aspect, the invention encompasses a circuitconstruction. The circuit construction includes a substrate having amemory array region and a region that is peripheral to the memory arrayregion. The circuit construction also includes a capacitor constructionover the memory array region of the substrate. The capacitorconstruction comprises a storage node, a dielectric layer and a cellplate layer. The dielectric layer is between the storage node and thecell plate layer. The circuit construction further includes anelectrical interconnect over the peripheral region. The interconnect iselectrically connected to the cell plate layer and extends between thecell plate layer and the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0008]FIG. 1 is a fragmentary, diagrammatic, cross-sectional view of asemiconductive wafer fragment at a preliminary processing step of amethod of the present invention.

[0009]FIG. 2 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 1.

[0010]FIG. 3 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 2.

[0011]FIG. 4 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 3.

[0012]FIG. 5 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 4.

[0013]FIG. 6 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 5.

[0014]FIG. 7 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 6.

[0015]FIG. 8 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 7.

[0016]FIG. 9 is a view of the FIG. 1 wafer fragment shown at a stepsubsequent to that of FIG. 6 in accordance with a second embodimentmethod of the present invention.

[0017]FIG. 10 is a view of the FIG. 9 wafer fragment shown at a stepsubsequent to that of FIG. 9.

[0018]FIG. 11 is a view of the FIG. 1 wafer fragment shown at a stepsubsequent to that of FIG. 3 in accordance with a third embodimentmethod of the present invention.

[0019]FIG. 12 is a view of the FIG. 11 wafer fragment shown at aprocessing step subsequent to that of FIG. 11.

[0020]FIG. 13 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 6 in accordance with a fourthembodiment method of the present invention.

[0021]FIG. 14 is a view of a semiconductive wafer fragment shown at aprocessing step subsequent to that of FIG. 2 in accordance with a fifthembodiment method of the present invention.

[0022]FIG. 15 is a view of the FIG. 14 wafer fragment shown at aprocessing step subsequent to that of FIG. 14.

[0023]FIG. 16 is a view of the FIG. 14 wafer fragment shown at aprocessing step subsequent to that of FIG. 15.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0025] In one aspect, the present invention encompasses a recognitionthat processing steps associated with the formation of circuitry over amemory array region of a semiconductive wafer substrate can beconsolidated with processing steps associated with formation ofcircuitry over a peripheral region of the substrate. Such will becomemore apparent with reference to FIGS. 1-6, which illustrate initialprocessing of a method of the present invention.

[0026] Referring initially to FIG. 1, a semiconductor wafer fragment 10comprises a semiconductive substrate 12. Substrate 12 can comprise, forexample, a monocrystalline silicon wafer lightly doped (i.e., doped to aconcentration of less than or equal to about 10¹⁶ atoms/cm³) with ap-type dopant. To aid in interpretation of the claims that follow, theterm “semiconductive substrate” is defined to mean any constructioncomprising semiconductive material, including, but not limited to, bulksemiconductive materials such as a semiconductive wafer (either alone orin assemblies comprising other materials thereon), and semiconductivematerial layers (either alone or in assemblies comprising othermaterials). The term “substrate” refers to any supporting structure,including, but not limited to, the semiconductive substrates describedabove. Semiconductive substrate 12 comprises a memory array region 14and a peripheral region 16.

[0027] Word lines 18, 20 and 22 are formed over substrate 12. Word lines18, 20 and 22 comprise a gate stack 24 and sidewall spacers 26. Gatestack 24 can comprise, for example, layers of silicon dioxide,polysilicon and silicide. Sidewall spacers 26 can comprise, for example,silicon nitride or silicon oxide.

[0028] Field oxide regions 28 are formed over substrate 12 within memoryarray region 14. Field oxide regions 28 can comprise, for example,silicon dioxide.

[0029] Electrical nodes 30 and 32 are defined adjacent word line 18, andelectrical nodes 34, 36 and 38 are defined adjacent word lines 20 and22. Wordlines 18, 20 and 22 can comprise transistors, and nodes 30, 32,34, 36 and 38 can comprise source/drain regions of such transistors.Nodes 30 and 32 are proximate peripheral region 16 of substrate 12. Theterm “proximate” indicates that nodes 30 and 32 can be within, above orbelow peripheral region 16 of substrate 12 (embodiments in which nodesare elevationally displaced from substrate 12 are not shown). Similarly,nodes 34, 36 and 38 are proximate memory array region 14 of substrate12. Nodes 30, 32, 34, 36 and 38 can comprise, for example, conductivediffusion regions formed within substrate 12. Such diffusion regions canbe formed by, for example, implanting conductivity-enhancing dopant intosubstrate 12.

[0030] An electrically insulative layer 40 is formed over substrate 12,and over word lines 18, 20 and 22. Insulative layer 40 can comprise, forexample, borophosphosilicate glass (BPSG), and can be formed by, forexample, chemical vapor deposition.

[0031] Referring to FIG. 2, openings 42 and 44 are etched throughinsulative layer 40 to nodes 34 and 38, respectively. Openings 42 and 44can be formed by, for example, providing a photoresist mask (not shown)over layer 40, and patterning the mask to expose regions of insulativelayer 40 at opening locations 42 and 44. Insulative layer 40 can then beetched with, for example, a fluorine-containing plasma to form openings42 and 44. The photoresist mask can be subsequently removed to leave thestructure shown in FIG. 2.

[0032] Referring to FIG. 3, capacitor storage nodes 46 and 48 are formedwithin openings 42 and 44 (FIG. 2), respectively. Capacitor storagenodes 46 and 48 can comprise, for example, polysilicon and preferablycomprise the shown roughened outer surfaces 50 and 52. Such roughenedouter surfaces can be formed by, for example, deposition ofhemispherical grain polysilicon.

[0033] A dielectric layer 54 is formed over storage nodes 46 and 48.Dielectric layer 54 can comprise, for example, one or more of silicondioxide or silicon nitride, and preferably comprises tantalum oxide.Dielectric layer 54 can be formed by, for example, chemical vapordeposition. Storage nodes 46 and 48, and dielectric layer 54, can beformed by methods known to persons of ordinary skill in the art, suchas, for example, chemical vapor deposition. In the shown embodiment, thematerial of storage nodes 46 and dielectric layer 54 does not extendover peripheral region 16. Such can be accomplished by, for example,masking peripheral region 16 while forming nodes 46 and 48, and whileforming dielectric layer 54.

[0034] Referring to FIG. 4, a photoresist masking layer 56 is providedover regions 14 and 16 of substrate 12 and patterned to define openings58 and 60 in peripheral region 16.

[0035] Referring to FIG. 5, openings 58 and 60 are extended to nodelocations 30 and 32, respectively. Openings 58 and 60 can be extendedby, for example, a plasma etch utilizing a fluorine-containingcomponent.

[0036] Referring to FIG. 6, photoresist material 56 (FIG. 5) is removed.Subsequently, a conductive material 62 is formed over both peripheralregion 16 and memory array region 14 of substrate 12. In the shownembodiment, conductive material 62 comprises two separate layers (64 and66). Layer 64 can comprise, for example, a metal nitride, such astitanium nitride or tungsten nitride, and layer 66 could comprise ametal such as tungsten, aluminum or copper. The metal of layer 66 can bein either an elemental form, or in the form of an alloy, such asaluminum/copper. Layers 64 and 66 can be formed by, for example,chemical vapor deposition and/or sputter deposition.

[0037] Layers 64 and 66 would typically have different functionalpurposes at peripheral region 16 relative to memory array region 14.Specifically, layers 64 and 66 form contact plugs 65 and 67 atperipheral region 16, with layer 64 preferably comprising a metalnitride and functioning as an adhesive layer for adhering metal layer 66within openings 58 and 60 (FIG. 5). Layer 64 can also function toprevent diffusion of dopant from diffusion regions 30 and 32 into metallayer 66. In contrast, layers 64 and 66 form at least a portion of acapacitor electrode 81 over memory array region 14. Specifically, layers64 and 66 together define at least a portion of capacitor cell plate 81,with conductive material 62 and dielectric layer 54 being operativelyadjacent storage node layers 46 and 48 to form capacitor structures 70and 72. In embodiments in which dielectric layer 54 comprises tantalumoxide, layer 64 preferably comprises a metal nitride. Layer 64 can thenfunction as a capacitor diffusion barrier layer to inhibit undesireddiffusion of materials between tantalum oxide layer 54 and uppercapacitor electrode layer 66.

[0038] Although material 62 is shown as comprising two layers, it is tobe understood that the invention also encompasses embodiments in whichmaterial 62 comprises only one layer, and other embodiments in whichmaterial 62 comprises more than two layers. For instance, material 62can comprise three layers wherein a first layer is titanium deposited toform titanium silicide at the bottoms of openings 58 and 60 (FIG. 5),and the remaining two layers are a metal nitride layer (such as TiN) anda metal layer (such as Al).

[0039] In the shown embodiment, conductive material layer 62 is formedover peripheral region 16 and memory array region 14 in a commondeposition step. Thus, such embodiment consolidates formation ofconductive contact plugs 65 and 67 with formation of capacitor electrode81 over memory array region 14. Such can save process steps relative toprior art methods which form conductive contacts over a peripheralregion of a substrate separately from formation of a capacitor electrodeover a memory array region of the substrate.

[0040] FIGS. 7-10 illustrate alternative processing methods which can beutilized for patterning conductive material at peripheral region 16.FIGS. 7-8 illustrate a first embodiment method, and FIGS. 9-10illustrate a second embodiment method. Referring first to the embodimentof FIGS. 7 and 8, and specifically referring first to FIG. 7, aphotoresist masking layer 76 is provided over memory array region 14while leaving peripheral region 16 exposed to an etching process. Theetch process removes conductive material 62 from over insulativematerial 40 at peripheral region 16 to electrically isolate conductiveplugs 65 and 67 from one another.

[0041] Referring to FIG. 8, a conductive layer 80 is formed over memoryarray region 14 and peripheral region 16 and patterned to form isolatedelectrical contacts with conductive plugs 65 and 67, and to form anotherportion of capacitor electrode 81 for capacitor constructions 70 and 72.More specifically, layer 80 and conductive material 62 together formcapacitor electrode 81 for capacitors 70 and 72. Conductive layer 80 cancomprise, for example, a metal such as tungsten, titanium, copper and/oraluminum, and can be formed by, for example, sputter deposition.Alternatively, conductive layer 80 can comprise a conductively dopedsemiconductive material, such as, for example, conductively dopedpolysilicon. Subsequent processing (not shown) such as provision of aninterlevel dielectric or spin-on-glass over one or both of regions 14and 16, followed by chemical-mechanical planarization can be conductedto form an insulative layer over regions 14 and 16.

[0042] Referring to the embodiment of FIGS. 9 and 10, identicalnumbering to that utilized in describing the embodiment of FIGS. 7 and 8will be used. A difference between the embodiment of FIGS. 9 and 10 andthat of FIGS. 7 and 8 is that in the FIGS. 9 and 10 embodimentconductive material 80 is formed over memory array region 14 andperipheral region 16 prior to etching of conductive material 62.

[0043] Referring initially to FIG. 9, conductive layer 80 has beenformed over memory array region 14 and peripheral region 16.

[0044] Referring to FIG. 10, conductive layer 80 and conductive material62 are patterned in a common etch to electrically isolate conductiveplugs 65 and 67 from one another, and to electrically isolate thecircuitry of peripheral region 16 from that of memory array region 14.The patterning of material 62 and layer 80 can comprise, for example,formation of a patterned photoresis: layer (not shown) over layer 80,and subsequent transferring of a pattern from the photoresist layer tounderlying layer 80 and conductive material 62 to form the structureshown in FIG. 10. The patterned photoresist layer forms a protectivelayer over a portion of conductive material 80 that is over storagenodes 46 and 48 that protects such portion of conductive material 80 asanother portion of conductive material 80 is removed from overperipheral region 16. The portion of conductive material 80 removed fromperipheral region 16 is proximate to where openings 58 and 60 (FIG. 5)were formed.

[0045] Another embodiment of the invention is described with referenceto FIGS. 11 and 12. In describing to FIGS. 11 and 12, identicalnumbering to that utilized above in describing FIGS. 1-10 will be used,with differences indicated by different numerals.

[0046] Referring first to FIG. 11, semiconductive wafer fragment 10 isshown at a processing step subsequent to that of FIG. 3, with a layer 90formed over dielectric layer 54 in memory array region 14, and extendingto over peripheral region 16. Layer 90 can comprise, for example, adiffusion barrier layer such as, for example, titanium nitride ortungsten nitride.

[0047] Referring to FIG. 12, openings are formed through layer 90 and tonode locations 30 and 32, and subsequently filled with conductivematerial 62. The formation of the openings and subsequent filling ofsuch openings with conductive material 62 can occur through processingsimilar to that described with reference to FIGS. 4-6. Wafer fragment 10of FIG. 12 can then be subjected to subsequent processing analogous tothat of either the embodiment of FIGS. 7-8 or the embodiment of FIGS.9-10 to form isolated conductive plugs in electrical contact with nodelocations 30 and 32, and to form capacitor structures similar to thestructures 70 and 72 of FIGS. 8 and 10.

[0048] Yet another embodiment of the present invention is described withreference to FIG. 13 which illustrates a semiconductive wafer fragment10 at a processing step subsequent to that of FIG. 9. In the FIG. 13embodiment, conductive layer 80 and conductive material 62 are patternedto electrically isolate contact plugs 65 and 67 from one another, butcontact plug 67 remains in electrical connection with the uppercapacitor electrode 81 over memory array region 14. Thus layers 64 and66 are common and continuous layers comprised by both contact plug 67and capacitors 70 and 72. In the FIG. 13 embodiment, contact plug 67forms an electrical connection between memory array region 14 andelectrical node 32.

[0049] The embodiment of FIG. 13 can be advantageous over prior artmethods for providing a good electrical contact to a cell plateelectrode. Specifically, prior art methods utilize electrical connectsextending upwardly from a cell plate layer. Such electrical connects areformed by providing an insulative layer over the cell plate layer andetching downwardly through the insulative layer to expose the cell platelayer. Occasionally, the etch extends through the cell plate layer andresults in a poor electrical connection to the cell plate layer. Incontrast, the embodiment of FIG. 13 utilizes an electrical connectionextending downwardly from a cell plate layer and formed during formationof the cell plate layer. Specifically, at least a portion of the cellplate layer 81 is preferably formed over electrical interconnect 67during formation of electrical interconnect 67.

[0050] It is noted that the invention also encompasses embodimentswherein cell plate layer 81 from memory array region 14 extends tophysically contact more than one contact plug in peripheral region 16.Such embodiments can provide redundancy in the event that one or more ofthe connections fails. In the shown embodiment, interconnects 65 and 67are connected through a switch comprising word line 18. Interconnect 65can then be connected to other circuitry (not shown) to provide aswitchable connection between such other circuitry and the capacitorplate 81 over memory region 14.

[0051] Yet another embodiment of the present invention is described withreference to FIGS. 14-16. In describing the embodiment of FIGS. 14-16,identical numbering to that utilized above in describing the embodimentsof FIGS. 1-13 will be used, with differences indicated by differentnumerals.

[0052] Referring to FIG. 14, wafer fragment 10 is illustrated at aprocessing step subsequent to that of FIG. 2. Specifically, storagenodes 46 and 48 are formed within openings 42 and 44 (FIG. 2). Waferfragment 10 of FIG. 14 differs from the wafer fragment 10 of FIG. 3(which is also at processing step subsequent to that of FIG. 2) in thatthere is no dielectric layer 54 provided over storage nodes 46 and 48 inthe embodiment of FIG. 14.

[0053]FIG. 15 illustrates the wafer fragment 10 of FIG. 14 after it hasbeen subjected to processing analogous to that described above withreference to FIGS. 4-6. Specifically, a conductive material 62 has beenformed over storage nodes 46 and 48. Conductive material 62 has alsobeen formed in electrical contact with node locations 32 to formelectrical interconnects 65 and 67 over peripheral region 16 ofsubstrate 12. As there was no dielectric layer formed prior to provisionof conductive material 62, material 62 electrically interconnects withnodes 46 and 48 to effectively become a portion of the capacitor storagenodes 46 and 48.

[0054] A patterned photoresist layer 100 is provided over peripheralregion 16 and memory array region 14. Patterned photoresist layer 100has openings 102 extending through it.

[0055] Referring to FIG. 16, openings 102 (FIG. 15) are extended toelectrically isolate electrical interconnects 65 and 67 from one anotherand from memory array region 14, as well as to electrically isolatestorage nodes 46 and 48 from one another. Photoresist layer 100 (FIG.15) is then removed, and a dielectric layer 54 is formed over memoryarray region 14. Dielectric layer 54 can be formed by, for example,processing described above with reference to FIG. 3. After formation ofdielectric layer 54, a conductive layer 80 is provide over storage nodes46 and 48, as well as over electrical interconnects 65 and 67.Conductive material 80 is then patterned to form a cell plate 81 overstorage nodes 46 and 48, and to form electrically isolated contacts tointerconnects 65 and 67. The formation and patterning of layer 80 can beconducted in accordance with the methods described above in reference toFIGS. 7 and 8.

[0056] The embodiment of FIGS. 14-16 forms a diffusion barrier layer 64that is part of capacitor storage nodes 46 and 48. In the shownembodiment, material 62 can comprise diffusion barrier componentsthroughout its thickness. Specifically, layers 64 and 66 can bothcomprise either titanium nitride or tungsten nitride.

[0057] It is noted that the embodiments described above form a diffusionbarrier layer as either part of a storage node, or as a part of acapacitor plate. The invention encompasses other embodiments (not shown)wherein one or more of the above-described embodiments are combined toform a diffusion barrier region as part of a storage node and to alsoform a diffusion barrier region as part of a capacitor plate.

[0058] It is also noted that there will typically be a bit line contact(not shown) formed in electrical connection with node 36 in theembodiments described above to connect node 36 to a bit line (notshown). Such bit line can be either above the capacitors (a so-calledcapacitor over bit line construction) or beneath at least a portion ofthe capacitors (a so-called capacitor over bit line construction).

[0059] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of forming circuitry comprising: forming a capacitorelectrode over one region of a substrate: forming a capacitor dielectriclayer proximate the electrode; providing a conductive diffusion barrierlayer between the electrode and the capacitor dielectric layer; forminga conductive plug over another region of the substrate, the conductiveplug comprising a same material as the conductive diffusion barrierlayer; and at least a portion of the conductive plug being formedsimultaneously with the conductive diffusion barrier layer.
 2. Themethod of claim 1 wherein the conductive diffusion barrier layercomprises a metal nitride.
 3. The method of claim 1 wherein theelectrode is a storage node of the capacitor.
 4. The method of claim 1wherein the conductive plug is formed within an opening in an insulativelayer and wherein the capacitor electrode is at least a portion of acapacitor cell plate, the method further comprising: before forming thecapacitor electrode, forming a storage node of the capacitor and formingthe capacitor dielectric layer over the storage node; forming aprotective layer over the capacitor dielectric layer before forming theopening in the insulative layer; protecting the capacitor dielectriclayer with the protective layer while forming the opening in theinsulative layer; and removing the protective layer before forming theconductive diffusion barrier layer.
 5. A method of forming circuitrycomprising the following steps: providing a substrate; defining a memoryarray region of the substrate and a peripheral region of the substrate,the peripheral region being peripheral to the memory array region;forming a capacitor construction over the memory array region of thesubstrate, the capacitor construction comprising a storage node, acapacitor dielectric layer, a capacitor barrier layer and a cell platelayer; the capacitor dielectric layer separating the storage node fromthe cell plate layer, the capacitor barrier layer separating thecapacitor dielectric layer from one of the storage node and the cellplate; forming an electrical interconnect over the peripheral region andin electrical connection with a doped region, the electricalinterconnect comprising a conductive interconnect barrier layer and ametal layer, the conductive interconnect barrier layer being between thedoped region and the metal layer; and wherein the conductiveinterconnect barrier layer and capacitor barrier layer are formed in asame step.
 6. The method of claim 5 wherein the capacitor barrier layerand conductive interconnect barrier layer comprise TiN.
 7. The method ofclaim 5 wherein the capacitor barrier layer and conductive interconnectbarrier layer comprise TiN, and wherein the same step comprises chemicalvapor deposition.
 8. The method of claim 5 wherein the capacitor barrierlayer and conductive interconnect barrier layer comprise TiN, andwherein the metal layer comprises one or more of Ti, W, Al and Cu.
 9. Amethod of forming circuitry, comprising: providing a substrate; defininga memory array region of the substrate and a peripheral region of thesubstrate, the peripheral region being peripheral to the memory arrayregion; forming a capacitor construction over the memory array region ofthe substrate, the capacitor construction comprising a storage node, acapacitor dielectric layer and a cell plate layer; the capacitordielectric layer separating the storage node from the cell plate layer;forming an electrical interconnect over the peripheral region, theinterconnect being electrically connected to the cell plate layer; andat least a portion of the interconnect being formed during, formation ofthe cell plate layer.
 10. The method of claim 9 wherein the forming theinterconnect and the cell plate layer comprises deposition of a commonand continuous conductive material over the peripheral and memory arrayregions of the substrate.
 11. The method of claim 9 wherein theinterconnect extends between the cell plate layer and the substrate toelectrically connect the cell plate layer to a node elevational belowthe cell plate layer.
 12. The method of claim 9 wherein the interconnectextends from the cell plate layer to the substrate to electricallyconnect the cell plate layer to a node within the substrate.
 13. Amethod of forming circuitry, comprising: providing a substrate; defininga memory array region of the substrate and a peripheral region of thesubstrate, the peripheral region being peripheral to the memory arrayregion; defining a first electrical node proximate the memory arrayregion of the substrate, and defining a second electrical node proximatethe peripheral region of the substrate; forming an electricallyinsulative layer over the substrate and over the electrical nodes;forming a first opening through the electrically insulative layer;forming at least a portion of a capacitor storage node within the firstopening and in electrical connection with the first electrical node;forming a second opening through the electrically insulative layer tothe second electrical node; in a common deposition step, forming aconductive material over the storage node and within the second openingin electrical connection with the second node; and forming a capacitordielectric layer and a capacitor electrode operatively adjacent thestorage node, one of the storage node or the capacitor electrodecomprising the conductive material.
 14. The method of claim 13 furthercomprising: forming a first layer over the storage node layer and overthe insulative layer before etching the second opening; and etching thesecond opening through the first layer.
 15. The method of claim 14wherein the first layer comprises at least one of TiN and WN.
 16. Themethod of claim 14 wherein the first layer comprises TiN.
 17. The methodof claim 14 further comprising forming the capacitor dielectric layerover the storage node layer before forming the first layer.
 18. Themethod of claim 14 further comprising: defining a third electrical nodeproximate the substrate, the third electrical node being proximate theperipheral region; forming the electrically insulative layer over thethird electrical node; simultaneously etching the second and thirdopenings through the first layer and through the insulative layer to thesecond and third electrical nodes, respectively; and in the commondeposition step, forming the conductive material within the thirdopening.
 19. The method of claim 13 wherein a portion of the conductivematerial overlies the insulative layer proximate the second opening, themethod further comprising: forming a protective layer over anotherportion of the conductive material that is over the storage node layer;and after forming the protective layer, removing the portion of theconductive material that overlies the insulative layer proximate thesecond opening.
 20. The method of claim 13 wherein the conductivematerial fills the second opening to form a conductive plug within thesecond opening, the method further comprising: forming the capacitordielectric layer over the storage node layer; forming a metal layer overthe conductive plug and over the storage node layer, the capacitordielectric layer being between the metal layer and the storage nodelayer, the metal layer comprising at least a portion of the cellelectrode layer; and patterning the metal layer to electrically separatea segment of the metal layer comprising at least the portion of the cellelectrode layer from a segment overlying the conductive plug.
 21. Themethod of claim 13 wherein the conductive material fills the secondopening to form a conductive plug within the second opening, the methodfurther comprising: forming the capacitor dielectric layer over thestorage node layer; and forming a metal layer over the conductive plugand over the storage node layer, the capacitor dielectric layer beingbetween the metal layer and the storage node layer, the metal layercomprising at least a portion of the cell electrode layer and beingelectrically connected to the second electrical node through theconductive plug.
 22. The method of claim 13 further comprising formingthe capacitor dielectric layer over the storage node layer prior toetching the second opening.
 23. The method of claim 13 wherein thesubstrate comprises monocrystalline silicon and the electrical nodescomprise electrically conductive diffusion regions formed within thesubstrate.
 24. The method of claim 13 wherein the forming the conductivematerial comprises forming a metal-comprising layer over the storagenode layer and within the second opening.
 25. The method of claim 13wherein the forming the conductive material comprises forming at leasttwo layers over the storage node layer and within the second opening.26. The method of claim 13 wherein the forming the conductive materialcomprises forming at least three layers over the storage node layer andwithin the second opening.
 27. The method of claim 13 wherein theforming the conductive material comprises: forming a layer comprisingTiN over the storage node layer and within the second opening; andforming a second layer over the layer comprising TiN, the second layernot comprising TiN.
 28. The method of claim 13 further comprising:defining a third electrical node proximate the substrate; forming theelectrically insulative layer over the third electrical node; etching athird opening through the insulative layer and to the third electricalnode while etching the second opening through the electricallyinsulative layer; and in the common deposition step, forming theconductive material within the third opening.
 29. The method of claim 28wherein the second and third nodes are electrically connected through atransistor.
 30. An integrated circuit comprising: a capacitor and aconductive plug, the conductive plug and capacitor comprising a firstcommon and continuous layer.
 31. The integrated circuit of claim 30wherein the first common and continuous layer comprises TiN.
 32. Theintegrated circuit of claim 30 wherein the conductive plug and capacitorfurther comprise a second common and continuous layer over the firstcommon and continuous layer.
 33. The integrated circuit of claim 32wherein the first common and continuous layer comprises a metal nitrideand the second common and continuous layer comprises a metal, the secondcommon and continuous layer being chemically different than the firstcommon and continuous layer.
 34. The integrated circuit of claim 30wherein the conductive plug and capacitor further comprise: a secondcommon and continuous layer over the first common and continuous layer;and a third common and continuous layer over the second common andcontinuous layer.
 35. The integrated circuit of claim 34 wherein thefirst common and continuous layer comprises Ti, the second common andcontinuous layer comprises a metal nitride, and the third common andcontinuous layer comprises one or more of W, Al and Cu; the first,second and third common and continuous layers being chemically differentfrom one another.
 36. The integrated circuit of claim 30 furthercomprising: a substrate; an insulative layer over the substrate; theconductive plug extending through the insulative layer; the capacitorcomprising a storage node extending through the insulative layer and acell electrode over the insulative layer; and the cell electrodecomprising the first common and continuous layer.
 37. The integratedcircuit of claim 36 wherein the first common and continuous layercomprises TiN.
 38. The integrated circuit of claim 36 wherein theconductive plug and the electrode layer further comprise a second commonand continuous layer over the first common and continuous layer.
 39. Theintegrated circuit of claim 36 wherein the conductive plug and cellelectrode further comprise: a second common and continuous layer overthe first common and continuous layer; and a third common and continuouslayer over the second common and continuous layer.
 40. A circuitconstruction comprising: a substrate having a memory array region and aperipheral region that is peripheral to the memory array region; acapacitor construction over the memory array region of the substrate,the capacitor construction comprising a storage node, a capacitordielectric layer and a cell plate layer; the capacitor dielectric layerbeing between the storage node and the cell plate layer; and anelectrical interconnect over the peripheral region, the interconnectbeing electrically connected to the cell plate layer and extendingbetween the cell plate layer and the substrate.
 41. The circuitconstruction of claim 40 wherein the electrical interconnect extendsfrom the cell plate layer to the substrate.
 42. The circuit constructionof claim 40 further comprising a transistor proximate the peripheralregion of the substrate, the transistor comprising a source/drainregion, the electrical interconnect extending from the cell plate layerto the source/drain region.
 43. The circuit construction of claim 40wherein the electrical interconnect and cell plate layer comprise atleast one common and continuous layer.
 44. The circuit construction ofclaim 40 wherein the electrical interconnect and cell plate layercomprise at least two common and continuous layers.
 45. The circuitconstruction of claim 40 wherein the electrical interconnect and cellplate layer comprise at least three common and continuous layers.